Junction field effect transistors (JFETs) are majority carrier devices that conduct current through a channel that is controlled by the application of a voltage to a p-n junction. JFETs may be constructed as p-channel or n-channel and may be operated as enhancement mode devices or depletion mode devices. Similar to the JFET is the metal-semiconductor field effect transistor (MESFET). In MESFETs, a junction between a metal and a semiconductor is used to create a Schottky barrier that takes the place of the p-n junction of the JFET.
The most common JFET type is the depletion mode type. The depletion mode device is a “normally on” device that is turned off by reverse biasing the p-n junction so that pinch-off occurs in the conduction channel. P-channel depletion mode devices are turned off by the application of a positive voltage between the gate and source (positive Vgs), whereas n-channel depletion mode devices are turned off by the application of a negative voltage between the gate and source (negative Vgs). Since the junction of a depletion mode JFET is reverse biased in normal operation, the input voltage Vgs, can be relatively high. However, the supply voltage between the drain and source (Vds) is usually relatively low when the device is turned on.
Prior Art FIG. 1 shows a general schematic for an n-channel depletion mode JFET with Vgs=Vds=0. The JFET has two opposed gate regions 10, a drain 11 and source 12. The drain 11 and source 12 are located in the n-doped region of the device and the gates 10 are p-doped. Two p-n junctions are present in the device, each having an associated depletion region 13. A conductive channel region 14 is shown between the two depletion regions 13 associated with the p-n junctions. In operation, the voltage variable width of the depletion regions 13 is used to control the effective cross-sectional area the of conductive channel region 14. The application of a voltage Vgs between the gates 10 and source 12 will cause the conductive channel region to vary in width, thereby controlling the resistance between the drain 11 and the source 12. A reverse bias, (e.g., a negative Vgs), will cause the depletion regions to expand, and at a sufficiently negative value cause the conductive channel to “pinch off”, thereby turning off the device.
The width of the depletion regions 13 and the conductive channel region 14 are determined by the width of the n-doped region and the dopant levels in the n-doped and p-doped regions. If the device shown in FIG. 1 were constructed with a narrow n-doped region, such that the two depletion regions merged into a single continuous depletion region and the conductive channel region 14 had zero width, the result would be the device shown in FIG. 2.
Enhancement mode, or “normally off” JFETs are characterized by a channel that is sufficiently narrow such that a depletion region at zero applied voltage extends across the entire width of the channel. Application of a forward bias reduces the width of the depletion region in the channel, thereby creating a conduction path in the channel. P-channel enhancement mode JFETs are turned on by the application of a negative Vgs, and n-channel enhancement mode JFETs are turned on by the application of a positive Vgs. The input gate voltage of an enhancement mode JFET is limited by the forward voltage of the p-n junction.
Prior Art FIG. 2 shows a general schematic of an n-channel enhancement mode JFET with Vgs=Vds=0. The enhancement mode device is “normally off” since the conductive channel width is zero due to the extent of the two depletion regions 13B. The application of a sufficient forward bias (e.g. positive Vgs) to the device of FIG. 2 will cause the depletion regions 13B to contract, thereby opening a conductive channel.
Although the depletion mode and enhancement mode devices shown schematically in FIG. 1 and FIG. 2 are n-channel devices, depletion mode and enhancement mode devices could be constructed with a reversed doping scheme to provide p-channel devices.
Historically, metal-oxide semiconductor field effect transistors (MOSFETs) have been much more widely used than JFETs, and among JFETs, the depletion mode device has been more widely used than the enhancement mode device. However, the adoption of submicron processes for device fabrication and the resulting higher speeds, lower voltages, and greater current demands in integrated circuits has created new opportunities for the application of JFETs.
JFETs are capable of being driven by low voltages while maintaining excellent breakdown characteristics when compared to MOSFETs. Since there is no insulator associated with gate/drain and gate/source interfaces of a JFET (only a p-n junction), forward bias results in conduction at a voltage that is very low compared to the reverse bias that the device is capable of withstanding. JFETs also have a much greater resistance to damage from electrostatic discharge (ESD) than MOSFETs.
The above mentioned characteristics of the JFET make it attractive for on-chip power conditioning in logic integrated circuits, and for power devices that incorporate control logic. However, when a JFET is integrated into another circuit, breakdown paths may be introduced that result in device failure below the intrinsic limits for a discrete JFET. As the electric fields that are responsible for breakdown increase with decreasing critical dimensions in semiconductor devices, the addition of structures such as guard rings becomes desirable.
Guard rings are used to alter the charge distribution and electric field at surfaces and material interfaces of semiconductor devices. The interface between the guard ring and the substrate in which it is embedded forms a depletion region that enhances resistance to breakdown in an applied field. Typically, guard rings used in bipolar and BiCMOS processes are fabricated by diffusion.
Prior Art FIG. 3A shows a cross-sectional view of a guard ring used to isolate a bipolar transistor. An n-type substrate 305 has an n+ layer 310 with a deposited collector contact 300. Within the n-type substrate is p-type well 320 forming the base of the transistor. The base 320 is connected to a base metal contact 335. Within the well 320 is an n+ region that forms the emitter 325 of the transistor. The emitter is connected to an emitter metal contact 340. Oxide 330 provides insulation at the surface of the device, and between the base metal contact 335 and the emitter metal contact 340. Two p-type guard rings 345 surround the base 320 and emitter 325.
Prior Art FIG. 3B shows a top view of the semiconductor structure of FIG. 3A without oxide or metallization. The guard rings 345 isolate the emitter 325 and the base 320 at the surface of the device. Diffusion processes are well suited to fabrication of guard rings for bipolar devices; however, the processes and geometries of guard rings used for bipolar devices are not fully compatible with the process and structures used for JFETs and MESFETs.